This commodity will explain some of the best important settings and architectonics ambit for the Xilinx FFT IP bulk and action as a basal walkthrough of the Fast Fourier Transform interface.

The Fast Fourier Transform (FFT) refers to a chic of algorithms that can calmly account the Discrete Fourier Transform (DFT) of a sequence. The DFT is a able apparatus in the assay and architectonics of agenda arresting processing systems and, consequently, the FFT is a frequently acclimated transform in a advanced ambit of DSP applications.

The FFT has a rather complicated algorithm and its accouterments accomplishing can be a challenge. That’s why altered FPGA vendors accept provided customizable FFT IP cores that can be added to a architectonics with aloof a few clicks. However, the artist still needs to apperceive some capacity about the FFT accouterments accomplishing afore actuality able to use these IP cores with confidence. There are abounding FFT IP cores to accept from. Intel has its own FFT IP Core, as does Lattice Semiconductor, and engineering firms such as Dillon Engineering. In this article, we will attending at the FFT IP bulk provided by Xilinx.

For a accepted altercation about amalgam a Xilinx IP bulk into your design, amuse see this commodity on the Xilinx CORDIC Core. This commodity will explain some of the important accomplishing ambit for the Xilinx FFT IP core, including what anniversary of these settings accomplishes for the engineer.

To add the FFT bulk to your ISE project, bang on “New Source” beneath the “Project” tab and accept “IP (CORE Generator & Architectonics Wizard)”. After giving your new antecedent a name and location, you can acquisition the FFT bulk by allotment “FFTs” from the “Digital Arresting Processing” category, as apparent in Bulk 1.

Then, a GUI will accessible which allows you to adapt the bulk according to your needs.

The aboriginal folio of the bulk settings is apparent in Bulk 2.

At the top of the page, we can accept the cardinal of channels for this core. This is advantageous back we charge to account the FFT of several altered signals. If all of these FFTs accept absolutely the aforementioned parameters, we can use one multi-channel FFT block instead of instantiating a single-channel FFT bulk several times in our HDL code. With a multi-channel implementation, some accouterments administration can be done by the amalgam apparatus and we can accept a added able design.

The bulk supports up to 12 channels. If a multi-channel bulk is chosen, some of the bulk ports, such as the FFT ascribe and achievement ports, will be bifold to board alive on assorted signals simultaneously. You can analysis the added ports by beat on the “IP Sym” tab in the bulk GUI (you can see this tab in the bottom-left bend of Bulk 2). Note that multi-channel operation is not accurate back the core’s “Implementation Options” is set to “Pipelined, Streaming I/O” (see Bulk 2).

The “Transform Length” specifies the breadth of the FFT transform. Its best bulk is 65536.

Next, we ability the “Implementation Options”. As apparent in Bulk 2, there are bristles altered options for the bulk implementation. The aboriginal advantage is “Automatically Select”. In this case, the software chooses the aboriginal accomplishing that meets the defined “Target Abstracts Throughput” for a accustomed “Target Alarm Frequency”.

Note that the “Target Alarm Frequency” and the “Target Abstracts Throughput” are alone acclimated to automatically baddest an accomplishing and account the architectonics latency. You can affix a alarm of any abundance to the alarm ascribe of the implemented FFT core. However, you will get a altered latency, if the absolute alarm abundance is altered from the one you specify in the bulk GUI. (Please appointment this appointment column folio for added information.)

As apparent in the figure, the added four accomplishing options are:

These options action a accommodation amid the bulk admeasurement and the throughput. This accommodation is depicted in Bulk 3. As a aphorism of thumb, the bulk admeasurement increases by a agency of two from one architectonics to the aing one in the figure.

The “Pipelined, Streaming I/O” accomplishing processes abstracts continuously. With this implementation, we can accompanying action the accepted anatomy of data, bulk the abstracts for the aing abstracts frame, and unload the after-effects of the antecedent abstracts frame. However, with “Radix-4, Burst I/O”, “Radix-2, Burst I/O”, and “Radix-2 Lite, Burst I/O”, the transform adding and the abstracts I/O cannot action simultaneously.

For these three implementations, we accept to aboriginal bulk a abstracts frame, account the transform, and again unload the result. Unloading the aftereffect of the accepted anatomy can be accompanying with loading the new abstracts anatomy alone if the abstracts is unloaded in a accurate adjustment alleged “bit/digit-reversed order”.

From the accomplishing point of view, it is easier to accomplish the achievement of the FFT algorithm in a accurate adjustment alleged bit/digit-reversed order.

As an example, accede a radix-2 eight-point FFT block that sequentially receives eight time-domain abstracts samples and again sequentially produces the FFT achievement values. We can administer the ascribe samples in the accustomed order, i.e., we aboriginal administer x[0], again x[1], again x[2], and so on; however, the FFT bulk may be advised to accomplish the achievement samples with the adjustment X[0], X[4], X[2], X[6], X[1], X[5], X[3], and X[7]. In this case, the bifold agnate of the basis of the generated achievement samples is 000, 100, 010, 110, …. These accord to the bit-reversed, or “mirrored,” versions of the accustomed indices (e.g., 000 becomes 000, 001 becomes 100, 010 becomes 010, 011 becomes 110, etc.).

That’s why we say that the achievement is in bit-reversed order. To see an archetype of the digit-reversed indices that a radix-4 FFT may generate, accredit to folio 6 of the Xilinx FFT bulk datasheet.

Generating the FFT outputs in bit/digit-reversed adjustment not alone makes the anamnesis acceptance of the architectonics added able but additionally decidedly simplifies the design. However, these advantages are accomplished at the bulk of accepting to aftermath the FFT achievement in bit/digit antipodal order. In this case, we’ll accept to accommodate the FFT achievement abstracts about in our calculations to aish the furnishings of bit/digit-reversed order. Refer to Area 9.2 of the book Discrete Time Arresting Processing for added details. Note that the accomplishing simplifications can be accomplished by authoritative either the ascribe or the achievement of the FFT bit/digit reversed; however, the Xilinx FFT bulk consistently receives the ascribe in the accustomed order.

The Xilinx FFT bulk achievement can be either in bit/digit-reversed adjustment or in accustomed order. Back accustomed adjustment achievement is selected, either added anamnesis assets will be activated or a time amends will be imposed, depending on which bulk accomplishing is selected.

The aftermost advantage of folio 1 is the “Run Time Configurable Transform Length”. Checking this advantage will accomplish the FFT breadth runtime configurable. In this case, two new ascribe ports, i.e., NFFT and NFFT_WE, will be added to the “IP Sym”. The NFFT is the ascribe that specifies the transform breadth at runtime, and NFFT_WE is the active-high address accredit for the NFFT input. We are accustomed to administer any bulk beneath than or according to the “Transform Length” that was alleged at the top of folio 1 of the bulk GUI. For example, a 1024-point FFT block will be able to compute transforms of lengths 1024, 512, 256, and so on. Allotment this advantage can access the bulk admeasurement and abate its best alarm frequency.

The additional folio of the bulk settings is apparent in Bulk 4.

In the “Data Format” section, we can specify the ascribe and achievement abstracts format, which can be either “Fixed Point” or IEEE-754 single-precision “Floating Point”. In the multi-channel approach of operation, the amphibian point architecture is not supported.

The aing area specifies the cardinal of $.25 acclimated to represent the “Input Data” and the “Phase Factor”. The “Phase Factor” refers to the connected algebraic coefficients that are assorted by the abstracts samples in the advance of the algorithm. As you can see, the “Input Abstracts Width” and the “Phase Agency Width” can be alleged independently.

Next, let’s attending at the “Scaling Options” section, which is accompanying to bit advance arising from the addition operations performed in the advance of the algorithm. To accretion some acumen into this issue, accede the arresting breeze blueprint of a radix-2 decimation-in-time eight-point FFT algorithm, as apparent in Bulk 5.

We can decompose this arresting breeze blueprint into baby units alleged a “Butterfly,” as apparent in Bulk 6.

The altered genitalia of the arresting breeze blueprint in Bulk 5 use the aloft erfly with altered appearance factors, $$W_{N}^{n}$$. The bulk of $$A^{‘}$$ and $$B^{‘}$$ can be begin from the afterward equations:

$$A^{‘} = A W_{N}^{n} B$$

$$B^{‘} = A – W_{N}^{n} B$$

The ambit in these two equations all can accept circuitous values. Hence, these two complex-valued equations will advance to four real-valued equations. It can be apparent that either the absolute or abstract allotment of $$A^{‘}$$ or $$B^{‘}$$ will abound by a agency of $$1 sqrt{2} approx 2.414$$ about to the absolute or abstract allotment of $$A$$ or $$B$$ i.e., the erfly ascribe signals. (See this TI appliance address for added information.) Considering the advance agency of 2.414 for a radix-2 erfly, we accept to access the amplitude of the registers autumn $$A^{‘}$$ and $$B^{‘}$$ by two $.25 compared to the amplitude of the registers acclimated for $$A$$ and $$B$$, contrarily overflow can occur, consistent in invalid calculations.

The “Scaling Options” area of the FFT bulk GUI provides altered means to accord with the botheration of overflow. We’ll briefly attending at the accurate options:

Unscaled

By allotment the “Unscaled” option, the amplitude of the registers will be alleged continued abundant to abstain overflow. This can use added FPGA assets in allegory with the “Scaled” advantage that will be discussed next. As mentioned above, a distinct radix-2 erfly requires a best bit advance of up to two $.25 to abstain overflow. However, not all of the FFT collywobbles will acquaintance this best bit growth. In fact, to accomplish full-precision unscaled addition after overflow, the Xilinx FFT IP bulk chooses the accumulation allotment of the FFT achievement such that it is according to (integer amplitude of the ascribe $$log_2(transform ; length)$$ 1) . For example, accept that we accept a 1024-point unscaled FFT bulk with 16-bit inputs, area 3 $.25 are allocated for the accumulation allotment and 13 $.25 for the apportioned part. In this case, the accumulation allotment of the achievement will accept 3 10 1=14 bits. The software will accomplish the amplitude of the apportioned allotment of the achievement according to that of the input. Hence, the FFT achievement will accept a absolute of 14 13=27 bits. Note that the accumulation amplitude is alleged to abstain overflow but the apportioned amplitude is alleged based on the adequate quantization error. Best of the IP cores abbreviate the apportioned allotment of the computations to ability a apportioned amplitude according to that of the bulk input.

Scaled

If we accept the “Scaled” option, we can administer a user-defined ascent agenda to the bulk calculations. In this case, the aftereffect of the altered stages of the algorithm will be disconnected (or right-shifted) by the user-defined ascent ethics so that overflow does not occur. For example, accept that we accept a 1024-point FFT block implemented application the “Radix-2, Burst I/O” structure. For this example, we accept $$log_2(point ; size) = log_2(1024)=10$$ radix-2 stages. Therefore, we’ll charge to accord the bulk 10 ascent ethics to ascendancy overflow. According to the Xilinx FFT bulk datasheet, we can use [01 01 01 01 01 01 01 01 01 10] as a bourgeois ascent agenda for this accurate example. This ascent agenda translates to a adapted about-face by 2 for date 0 of the algorithm and a adapted about-face by 1 for the nine actual stages. In added words, the two LSB $.25 accord the ascent bulk for date 0, the aing two $.25 accord the ascent bulk for date 1, and so on. These ascent ethics can be activated to the ascent agenda ascribe for the core, i.e., SCALE_SCH, which becomes alive back the “Scaled” advantage is selected. Note that, with a accustomed ascribe type, it can be difficult to acquisition the minimum ascent bulk for anniversary FFT date that prevents from overflow. That’s why Xilinx has developed a C archetypal that can be acclimated to acquisition an adapted ascent agenda for a accustomed aberration akin in the ascribe signal. Accredit to folio 21 of the FFT bulk datasheet for added advice about application this C model.

Block Amphibian Point

“Block Amphibian Point” is the aing advantage for alienated the overflow problem. Back the FFT ascribe is not able-bodied accepted and can display ample fluctuations, a “Scaled” anatomy may not be successful. In such cases, “Block Amphibian Point” can be used. This advantage prevents overflow by acceptance the bulk to actuate the adapted ascent bulk for the altered stages of the algorithm. The bulk of ascent activated will be appear as a block backer by the BLK_EXP achievement of the core. “Block Amphibian Point” approach may crave decidedly added assets compared to an accomplishing that uses “Scaled” mode.

For added advice about the aftereffect of bound annals breadth on FFT performance, amuse accredit to Area 9.7 of Discrete Time Arresting Processing.

The “Rounding Modes” in folio 2 of the bulk GUI specifies the address acclimated to abate the apportioned amplitude of the erfly computations. There are two options: “Truncation” and “Convergent Rounding”. The “Truncation” adjustment is simpler and uses beneath accouterments resources; however, “Convergent Rounding” avoids the DC bent alien by “Truncation”.

The “Optional Pins” area allows us to add some alternative pins, such as Alarm Accredit (CE) and Synchronous Clear (SCLR), to the core.

The “Output Ordering” advantage specifies whether the achievement will be generated in “Natural Order” or “Bit/Digit Antipodal Order”.

“Input Abstracts Timing” is an advantage included to accomplish the bulk accordant with its beforehand versions. For a new design, you can accept “No Offset”.

Page 3 of the settings is apparent in Bulk 7.

This aftermost folio of the settings specifies some accomplishing options. We can adviser the bulk to use the FPGA resources, such as the Block RAMs, Distributed RAMs, or DSP slices, according to our project’s requirements. Since these options are adequately straightforward, we won’t go through the details. Amuse accredit to the bulk datasheet to apprentice about application these options correctly.

After allegorical all these parameters, we can accomplish the bulk and add it to our design. Now that you accept some acumen into the altered options of the Xilinx FFT core, you should be able to added calmly the actual covered in the bulk datasheet. Remember that you’ll charge to carefully investigate the bulk timing diagrams afore you can use it accurately in your design!

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