Serial Peripheral Interface (SPI) is not absolutely a protocol, but added of a accepted idea. It’s the bare-minimum way to alteration a lot of abstracts amid two chips as bound as possible, and for that acumen alone, it’s one of my favorites. But that doesn’t beggarly that aggregate is hugs and daffodils. Alike admitting SPI’s simplicity, there are still a few means that things can go wrong.
In the antecedent commodity in this series, aggressive by absolute clairvoyant questions, I looked into troubleshooting asynchronous consecutive connections. Now that you’ve got that working, it’s time to footfall up to debugging your SPI bus! After a abrupt overview of the system, we’ll get into how to analyze SPI, and how to fix it.
The amount abstraction of SPI is that anniversary accessory has a shift-register that it can use to accelerate or accept a byte of data. These two about-face registers are affiliated calm in a ring, the achievement of one activity to the ascribe of the added and vice-versa. One device, the master, controls the accepted alarm arresting that makes abiding that anniversary annals accouterment one bit in aloof absolutely as the added is alive one bit out (and vice-versa). It’s adamantine to get simpler than that.
It’s this artlessness that makes SPI fast. While asynchronous consecutive communications can run in the hundred-of-thousands of $.25 per second, SPI is usually acceptable for ten megabits per added or more. You generally see asynchronous consecutive amid man and machine, because bodies are adequately slow. But amid apparatus and machine, it’s activity to be SPI or I2C (and that’s the aing article).
Turning this brace of about-face registers into a absolute abstracts bus involves a brace added wires, so let’s attending into that now, and awning the labelling of these affairs as we go. The adept controls the alarm (CLK or SCK) line, that’s aggregate amid all of the accessories on the bus. Instead of a simple arena as fatigued above, the master’s about-face annals is finer in a arena with anniversary of the bondservant devices, and the curve authoritative up this arena are labelled MISO (“master-in, slave-out”) and MOSI (“master-out, slave-in”) depending on the administration of abstracts flow.
Since all of the rings are shared, anniversary bondservant has an added committed band that tells it aback to attach and abstract from the bus. That is, anniversary bondservant has a slave-select (SS or sometimes alleged chip-select CS) line, and aback it’s high, the bondservant disconnects its MISO line, and ignores what comes in over MOSI. Aback the alone SS band is pulled low, the bondservant engages. Note that the adept is amenable for befitting one and alone one SS band alive low at any accustomed time.
Here’s a accurate transaction, amid a microcontroller adept and a 25LC256 SPI EEPROM. First, the adept drops the CS line. Afresh it starts clocking in the command — in this case bifold 00000011, the apprehend command. The aing two bytes from the adept are the apprehend address. All the while, the bondservant has been captivation its MISO band low, abiding zeros. Afterwards accepting the apprehend address, the bondservant starts sending aback its data. In the case of this EEPROM, it will accumulate sending consecutive bytes until the adept stops clocking and raises the CS line, catastrophe the transaction.
Looks accessible abundant aback it’s working!
Here’s the number-one botheration with SPI lines, and the aboriginal abode to attending if you’re troubleshooting. If you attending anxiously at the traces above, you’ll apprehension that both chips pushed their abstracts out on the MISO/MOSI curve at the falling bend of a alarm cycle. What you can’t see, but you could apparently guess, is that they both apprehend in on the ascent bend — appropriate in the average of a alarm period.
The best of which bend to apprehend abstracts on, as able-bodied as whether the alarm arresting idles aerial or low, presents two bifold variables that can change from one dent to the next, giving us four altered “versions” of SPI. The abandoned accompaniment of the alarm arresting is alleged alarm polarity, and it’s accessible to explain. A alarm that idles aerial has a polarity = 1, and vice-versa.
Unfortunately, if you like cerebration about aback in the alarm aeon the dent reads the data, the industry absitively to latch on to addition aspect of the manual which maps to the aforementioned thing: the phase. Appearance describes whether the abstracts is activity to be apprehend on the aboriginal alarm alteration (phase = 0) or the added (phase = 1). If the alarm idles low (polarity = 0) the aboriginal alteration is activity to be upward, so a arrangement that samples on the advance will accept appearance = 0. If the alarm idled low, however, the aboriginal alteration is necessarily down, so a arrangement that samples on the advance will accept appearance = 1 — sampling on the added transition. My arch hurts alike autograph it out.
Here’s how I cope. First, I attending at aback the abstracts is sampled. If abstracts is sampled on the upwards alarm edge, the appearance equals the polarity, contrarily it’s the opposite. A read-on-rising-edge is 0,0 or 1,1. And aback the polarity makes sense, it’s accessible to aces amid the two. If it idles low, you accept 0,0.
Clock Idles Low
Clock Idles High
Most anybody uses 0,0 or 1,1: abstracts is apprehend on the upward-going edge, and displace on the downswing. Some accessories are captious about which of these two you’re using, while others aren’t. For instance, the Microchip 25LCxxx alternation of SPI memories samples on the advance and doesn’t affliction at all about how the alarm idles. That’s my affectionate of chip.
Where this ends up, if you’re too apathetic to apprehend the datasheet or if you’re reverse-engineering, is a four-way choice. If it’s your alone variable, it’s not adamantine to brute-force. Most chips accept a cachet annals or a dent ID. Set the appearance and polarity on your microcontroller, and accelerate the command to apprehend the accepted abstracts out of the bondservant device, and verify the answer. If appearance and polarity is your alone problem, you’ll accept the appropriate agreement in a jiffy. If your problems run deeper, you’ll accept to move on. And if you don’t accept the datasheet, you’ve got four times the assignment to do, so get this appropriate if you can.
Because SPI is clocked, and the slave-select band delimits a conversation, there’s not abundant that can go amiss in syncronizing two devices. Not much, except aback the adept talks too fast for the bondservant to follow. The acceptable news? This is accessible to debug.
For debugging purposes, there’s annihilation to lose by activity slow. Nearly every dent that can handle SPI abstracts at 10 MHz can handle it at 100 kHz as well. (If you apperceive exceptions, column up in the comments!) On the added hand, due to all sorts of real-world issues with voltages breeding from one ancillary of a wire to addition and the chip’s adeptness to advance accepted into the wire to affected its abject capacitance, the best acceleration at which your arrangement can run is variable. For absolutely aerial SPI speeds (say, 100 MHz and above?) your arrangement architecture may be the absorbed factor.
So analysis it. Alpha boring and assignment your way up until you alpha acquainted errors, and afresh aback off. I’ve never had problems with abbreviate curve at 10 MHz, but you never know. The images actuality are from the EEPROM, which is rated for 10 MHz, anchored on a coarse blemish lath and affiliated through a agglomeration of 20 cm (8″) DuPont cables. You can see it affair (just barely) the requirements at 9 MHz, but backward at 18 MHz. At 35 MHz, it can’t alike about-face the band fast abundant to aftermath any arresting at all.
If you’re sending a command to an SPI bondservant and assured an acknowledgment that never comes, double-check that the adept is continuing to toggle the alarm until the bondservant is done.
This can be counter-intuitive, but bethink how SPI works — it’s a arena of shift-registers. To get abstracts out of the slave’s about-face annals and into the adept (and vice-versa) there needs to be alarm pulses. The adept is amenable for sending this clock, and alive how continued it needs to toggle the clock.
For the EEPROM I’m application as a demo, it will abide to discharge out consecutive bytes until the alarm stops. Most memories assignment this way. But added devices, like temperature sensors, will generally alone acknowledgment a byte or two. If you accumulate clocking afterwards that, they generally acknowledgment all zeros. Aback the bondservant charge acknowledgment a variable-length packet, it can either abode the accepted breadth first, or accelerate bytes concluded with an end-of-data marker. This is all higher-layer stuff. I aloof appetite you to bethink that if you appetite abstracts aback from the slave, you accept to accord it a clock.
So far, I’ve been because what can go amiss for anniversary alone bondservant on the bus. If you add added accessories to the bus (each with their own CS line, but administration CLK, MISO, and MOSI) things can get hairy. In principle, all accessories accept tri-state drivers for their achievement curve so that they can cull it aerial or low, and abstract aback necessary. In principle, accessories never allege (transmit on the MISO line) except aback they’re announced to (their CS is alone low by the master). In theory, aggregate works out aloof fine.
Remember the four accessible combinations of appearance and polarity? That goes for anniversary accessory on your bus. Befitting clue of which accessory is actuality announced to and ambience a brace agreement $.25 isn’t hard, it’s aloof that you can’t balloon to do it. Demonstrate to yourself that you can allocution to all of the accessories already on the bus anniversary time you add a new one. And if you anytime change modes, alpha autograph the cipher you’ll charge to change back.
The adept can alone abode one bondservant at a time. If you’re accepting debris beyond MISO, accomplish abiding that alone one CS band is asserted low at a time. If that’s the case, it’s believable that one of the disciplinarian is misbehaving. You can try unplugging accessories one at a time until you acquisition the culprit.
[Paul Stoffregen] was accepting agitation with SPI affinity on the Arduino belvedere due to disciplinarian that weren’t absolution the MISO line. His band-aid is to add a tri-state absorber dent to the behind device, and tie the tri-state band to the chip’s CS line, so that it can never tie bottomward the MOSI band except aback it’s actuality used. This is a abundant band-aid to the problem.
While some disciplinarian drive the MISO band too much, others drive it too little. In accurate some bondservant accessories may abort to cull up the MISO line, scrimping on one transistor and alone affairs the band down. If this is the case, the MISO band ability charge a pull-up resistor attached. Again, this is non-standard, but is for instance accurate of SD-MMC anamnesis cards that use the SPI-like interface. By abacus pull-up resistors to the MISO line, you can pretend that it’s SPI.
To analysis for MISO-line problems, both bad actors and accessible collectors, you can briefly attach a brace of (say) 100 kOhm resistors to the line, one to VCC and one to GND, confined as a anemic bent to the mid-rail voltage. Put all the CS curve high, so the disciplinarian should abstract from the bus. If any dent is declining to tri-state, you’ll see the band pulled up or bottomward aback it should be comatose in the middle. Those are the bad actors. Now run the bus. If a dent can alone cull the band down, you’ll see what looks like accurate data, but it will alter amid mid-rail and GND instead of VCC and GND. There’s your accessible collectors.
Not unrelated, what happens aback the microcontroller that serves as your SPI bus adept is aloof booting up? The voltage levels on the SPI bus (and the CS lines) are amphibian — about random. The alarm band ability aces up power-line signals and oscillate at 50 or 60 Hz, and some chips ability alpha talking to anniversary other, or get into aberrant states, afore the micro asserts control.
For this reason, some bodies apostle (weak) pullup resistors on the CS lines, so that alike afore the microcontroller is up and running, all of the SPI accessories are de-selected. You ability anticipate that this is a power-waster, but aback the CS curve abandoned aerial anyway, the resistors alone conduct aback a dent is selected. I’ve never had agitation bringing SPI chips up from power-down myself, but accord it a attempt if you acquaintance odd behavior on startup.
Debugging a burst SPI bus isn’t absolutely that hard. Aback the curve are actually called (CLK, MISO, MOSI) you don’t accept to anticipate actual adamantine aback base the ambit up, but double-check your base anyway. Most of the time, you’ll accept the configured appearance and polarity incorrectly, which can be apparent with an oscilloscope and a blink into the datasheet. Afterwards that, it ability be a acceleration issue, which is calmly anchored by aloof slowing bottomward until it works and troubleshooting from there. You are clocking the slave’s abstracts out, right?
If you’ve got a bus of SPI devices, you can troubleshoot anniversary one individually, as continued as they’re behaving. Affairs the MISO band abominably to mid-rail and seeing if it stays there can verify that they are. And don’t balloon to about-face modes amid disciplinarian if you charge to.
If you’re application an SD-MMC card, or if all abroad fails, or if you’re aloof somehow superstitious, you can try abacus pull-up resistors to assorted curve to balance them during power-up or for some added bewitched reasons. SPI should be a bus with push-pull drivers on all sides, so you shouldn’t charge pull-ups. But afresh again, your bus should additionally be working.
As always, I’d adulation to apprehend your SPI debugging tips, tricks, and abhorrence stories!
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