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Some applications crave the ecology of ability activated to a system. Microchip Technology addressed this charge with the MCP39F511A, a awful integrated, single-phase power-monitoring IC advised for real-time altitude of ac and dc inputs. It detects the ascribe voltage and automatically sets operation in the adapted mode, either dc or ac.

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Separate ac and dc arrangement registers advice ensure high-accuracy abstracts in both modes. An chip 7-ppm/°C voltage advertence and 94.5-dB signal-to-noise and baloney arrangement (SINAD) achievement are alive in anniversary mode. The IC provides 0.1% accurateness over a 4000:1 activating range. Housed in a 28-lead 5×5 QFN package, it has an operating temperature ambit of −40 to 125°C. Figure 1 shows a simplified block diagram of the MCP39F511A.

1. Shown is a simplified block diagram of the MCP39F511A.

The MCP39F511A includes an asynchronous full-duplex UART with eight Alpha and Stop $.25 and a absence baud amount of 9.6 kb/s. The Simple Sensor Interface (SSI) agreement is acclimated for point-to-point advice from a single-host microcontroller (MCU) to a single-slave MCP39F511A. The UART advice provides the ecology abstracts to the MCU, which can be displayed on a adviser or printed out.

All advice to the MCP39F511A occurs in frames that abide of a attack byte, the cardinal of bytes in the frame, command packet (or command packets), and a checksum. The best cardinal of bytes for either a accept or address anatomy is 35 (Fig. 2). This access allows for single, defended manual from the host processor to the MCP39F511A with either a distinct command or assorted commands.

2. Communications to the MCP39F511A action in frames.

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After the accession of a advice frame, the MCP39F511A has three accessible responses, which will be alternate with or after abstracts depending on the anatomy received. These responses are:

 A account of all accustomed command bytes for the MCP39F511A includes:

Coherent Sampling Algorithm

The MCP39F511Auses a articular sampling algorithm to appearance lock the sampling amount to the band abundance with an accession cardinal of samples per band aeon (56) and letters all ability achievement quantities at a 2N cardinal of band cycles. Authentic as a ciphering cycle, it’s abased on the band frequency. Thus, any change in the band abundance will additionally change the amend amount of the ability outputs.

Assuming that the ascribe abundance is 60 Hz, the sampling acceleration is 56 × 60 = 3360 samples/s. For the absence accession breach constant of 2, the computational aeon is 56 × 4 disconnected by the sampling acceleration (the aftereffect is 66.66 ms). In dc mode, the sampling acceleration is anchored at about 1953 samples/s. For the absence amount of the accession breach constant (2), the computational aeon is 56 × 4 disconnected by the sampling acceleration (the aftereffect is about 114.7 ms).

The articular sampling algorithm is additionally acclimated to account the Band Abundance Achievement register, which is adapted every ciphering cycle. The alteration agency for band abundance altitude is the Accretion Band Abundance register, which is acclimated during the band abundance calibration. The resolution of the Band Abundance Achievement annals is fixed, and the resolution is 1 mHz.

At Power-on Reset, the adding agent charge initialize the analog advanced end (AFE) and initialize all of the peripherals above-mentioned to actuality able to alpha the aboriginal ciphering cycle. In addition, the accessory charge ascertain whether or not an ac arresting is present; if so, it charge actuate the actual articular sampling alarm values. This action is accustomed acceptable time for actual initialization; the startup time is 417 ms for a 60-Hz line.

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Its high-pass filters are angry off to let canyon both dc and ac signals. If the cardinal of aught crossings detected during this time on the voltage approach is beneath than 10 (to clarify out apocryphal detections), the accessory will automatically about-face to dc mode.

An centralized adverse based on the sampling amount of the AFE determines if an ac arresting isn’t present and if the accessory should about-face to dc mode. If an ac arresting isn’t present for this time aeon (same as above, based on the cardinal of aught crossings detected on the voltage channel), the accessory will about-face to dc mode, axis off the high-pass filters and ambience the abundance achievement to zero.

The accession breach is authentic as a 2N cardinal of band cycles, area N is the amount in the Accession Breach Constant register. N can be as low as 0 (for the fastest amend rate), but no bigger than 8.

Several registers are acclimated to abundance data, including:

RMS Measurements

The MCP39F511A provides authentic RMS measurements. It has two accompanying sampling 24-bit A/D converters for the accepted and voltage measurements. The basis beggarly aboveboard calculations are performed on 2N accepted and voltage samples, area N is authentic by the annals Accession Breach Parameter

For alive and acknowledging power, acceptation and consign registers for alive energy, and four-quadrant acknowledging ability altitude the MCP39F511A offers alive ability numbers. Acceptation ability or activity is advised absolute (power or activity actuality captivated by the load), and consign ability or activity is advised abrogating (power or activity actuality delivered by the load).

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Energy accession for all four activity registers (Import/Export, Active/Reactive) occurs at the end of anniversary ciphering cycle, if the activity accession has been angry on. A no-load beginning analysis is done to accomplish abiding the abstinent activity is not beneath the no-load threshold, if it is above, the accession occurs with a absence activity resolution of 1 mWh for all of the activity registers.

The no-load beginning is set by modifying the amount in the No-Load Beginning register. The assemblage for this annals is ability with a absence resolution of 0.01W. The absence amount is 100 or 1.00W. Any ability that is beneath 1W will not be accumulated into any of the activity registers.

A 32-bit annals food the final credible ability indication. It is the artefact of RMS accepted and RMS voltage. For ascent of the credible ability indication, the adding agent uses the annals Credible Ability Divisor Digits.

For the alive ability calculation, the direct accepted and direct voltages are assorted calm to actualize direct power.

This direct ability is again adapted to alive ability by averaging or artful the DC component.  Although this annals is unsigned, the administration of the alive ability (import or export) can be bent by the Alive Ability Assurance bit amid in the Arrangement Status Register.

Power agency is affected by the arrangement of alive ability disconnected by credible power. The ability agency account is stored in a alive 16-bit annals (Power Factor). This annals is a signed, 2’s accompaniment annals with the MSB apery the polarity of the ability factor. A absolute ability agency agency Alive ability is actuality imported, a abrogating ability agency represents consign alive power. The assurance of the acknowledging ability basic is acclimated to acquaint if the accepted is backward the voltage, with a absolute assurance acceptation an anterior amount and a abrogating assurance acceptation capacitive. Anniversary LSB is again agnate to a weight of 2-15.

Reactive ability is affected application a 90 amount appearance about-face in the voltage channel. The aforementioned accession attempt administer as with alive ability area ACCU acts as the accumulator. Any ablaze amount or balance ability can be removed by application the Account Acknowledging Ability register. Accretion is adapted by the Accretion Acknowledging Ability register. The final achievement is an bearding 32-bit amount amid in the Acknowledging Ability register. This annals is unsigned, the administration of the ability can be bent by the Acknowledging Ability Assurance bit in the arrangement Status register.

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Pulse Width Modulation

The PWM achievement pin gives up to a 10-bit resolution of a PWM signal. The PWM achievement is controlled by an centralized timer central the MCP39F511A, FTIMER, with a base

frequency of 16 MHz. The abject aeon is authentic as PTIMER and is 1/[16 MHz]. This 16-MHz time abject is anchored due to the 4-MHz centralized oscillator or 4-MHz alien quartz crystal.

Two registers ascendancy the PWM output, PWM period, and PWM assignment cycle. The 8-bit PWM aeon is controlled by a 16-bit annals that contains the aeon $.25 as able-bodied as the prescaler bits. The PWM aeon $.25 are the best cogent eight $.25 in the register; the prescaler amount is represented by the atomic two cogent bits. These two ethics calm actualize the PWM period. The 10-bit PWM assignment aeon is controlled by a 16-bit annals area the eight best cogent $.25 are the 8 MSBs and the 2 LSBs, agnate to the 2 LSBs of the 10-bit value.

Calibration

Calibration compensates for the ADC accretion error, basic tolerances, and all-embracing babble in the system. The accessory provides an on-chip arrangement algorithm that enables simple arrangement arrangement to be performed quickly. The accomplished analog achievement of the ADCs on the MCP39F511Aallows for a single-point arrangement and a distinct arrangement command to accomplish authentic abstracts in ac mode. In dc mode, account arrangement is usually required.

Calibration can be done by either application the predefined auto-calibration commands, or by autograph anon to the arrangement registers. If added arrangement credibility are appropriate (ac offset, appearance compensation, dc offset), the agnate arrangement registers are available.

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Power Adviser Demonstration Board

The MCP39F511A Ability Adviser Demonstration Lath is a absolutely functional, single-phase ability and activity adviser (Fig. 3). The arrangement calculates alive power, acknowledging power, RMS current, RMS voltage, alive activity (both acceptation and export), acknowledging energy, and added archetypal ability quantities.

3. The MCP39F511A single-phase ability and activity adviser audience lath has an centralized 3.3-V switching ability accumulation and abandoned UART inputs from the MCU.

This Ability Adviser Demonstration Lath uses the Ability Adviser Utility software for appraisal through a USB affiliation to the board. The Utility software is acclimated to calibrate and adviser the system, and can be acclimated to actualize custom arrangement setups. For best accurateness requirements, alone a single-point arrangement is needed. The software offers an automatic step-by-step arrangement action that can be acclimated to bound calibrate ability meters.

The Demonstration Lath operates from 90 to 230 V rms. The high-voltage band and aloof access are amid at the basal of the board. The blow sits on the aloof or the low ancillary of a two-wire system.

The lath comes busy with a surface-mount 2-mΩ shunt. When application a lower amount alien shunt, aberration calm the affairs activity from the alien blow to the CP1 and CP2 connections. The high-voltage ancillary of the two-wire arrangement goes into a resistor affiliate on the voltage-channel input. Anti-aliasing low-pass filters are amid on the ascribe pins. The voltage approach uses two 499-kΩ resistors to accomplish a affiliate arrangement of 1000:1. For a band voltage of 220 V rms, the approach 1 ascribe arresting admeasurement is 220 mV rms.

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