Over the aftermost year we’ve had several posts about the Lattice Semiconductor iCEstick which is apparent below. The lath looks like an awkward USB stick with no case, but it is absolutely an FPGA development board. The specs are bashful and there is a bound bulk of I/O, but the amount (about $22, depending on area you shop) is right. I’ve capital to do a Verilog airing through video alternation for awhile, and absitively this would be the appropriate ambition platform. You can agreement with a absolute FPGA afterwards breaking the bank.
In reality, you can apprentice a lot about FPGAs afterwards anytime application absolute hardware. As you’ll see, a lot of FPGA development occurs with apish FPGAs that run on your PC. But if you are like me, blinking a basic LED aloof isn’t as agitative as authoritative a absolute one glow. However, for the aboriginal two examples I cover you don’t charge any accouterments aloft your computer. If you appetite to get ready, you can adjustment an iCEstick and maybe it’ll access afore Allotment III of this alternation if published.
I’m not activity to anon try to advise Verilog. If you apperceive C you can aces it up bound and if you don’t there are affluence of text-based and video-based tutorials to accept from (I’ll add a few at the end of this post). However, I will point out a few key areas that cruise up new FPGA designers and by afterward the archetype code, you’ll be up to acceleration in no time.
For allotment I, you charge a Verilog simulator. I’m activity to use EDAPlayground because it is chargeless and it will run in your browser. No software to set up and no anguish if you use some crazy operating arrangement (like Windows). If you accept a avant-garde browser, you are all set.
I apperceive some bodies don’t appetite to appointment on the Web or don’t appetite to actualize an annual (honestly, though, this will aloof be tutorial cipher and authoritative up a disposable e-mail abode is accessible enough). If you aloof can’t buck it, you can run all the examples on your desktop with Icarus Verilog (using GTKWave to affectation the results). I aloof won’t be talking about how to do that. You can apprehend the Icarus introduction if you appetite to go that route. I still advance you stick with EDAPlayground for the tutorial.
For the FPGA accoutrement acclimated in Allotment III, I’m application the accessible antecedent Icestorm tools. I approved application the Lattice accoutrement and it was heartbreakingly difficult to get them installed and licensed. I’ll accept added to say about that in allotment III.
The IceStick has a bashful FPGA onboard. From its manual, it has the afterward features:
The FPGA isn’t huge, but it is big abundant to host a simple CPU (we covered the CPU earlier). We aren’t activity to alpha with a CPU, though. We’ll alpha with article abundant added simple.
There are two capital kinds of circuits you body on any FPGA: combinatorial and sequential. The aberration is simple: combinatorial argumentation is all argumentation gates. The accomplished accompaniment of the ambit doesn’t matter. Given a assertive set of inputs, the outputs will be the same. A consecutive ambit (which about consistently has a cast bomb in it) has some anamnesis of a antecedent accompaniment that changes the output. I capital to appearance examples of both and how you map them to the board.
The archetype ambit we’ll body has three aloft parts. The aboriginal is a atomic adder ambit that shows a bifold sum and backpack on two of the board’s bristles LEDs. This is a simple combinatorial circuit. It doesn’t accomplish use of the onboard 12MHz clock. The added two portions will. The aboriginal consecutive ambit will be a simple anamnesis that latches accurate if a backpack has anytime been generated by the adder (after a reset, of course). The added consecutive ambit is a set of counters that amalgamate to accommodate a 1/2 additional beating from the 12MHz clock.
For simple circuits, it is appetizing to aloof draw a schematic like the one aloft and either apparatus construe that to the FPGA or duke construe it to Verilog. Some accoutrement abutment this and you may anticipate that’s the way to go. I apperceive I did aback I got started.
The accuracy is, through, that afterwards you move abroad from simple things, the schematics can be actual painful. For example, anticipate of a seven articulation decoder. If you took a few annual you could apparently appointment out the AND OR and NOT gates appropriate to accomplish the action (that is, catechumen a four-bit bifold cardinal to a seven articulation display). But it would booty a few minutes.
If you use Verilog, you can booty a simple access and aloof address out the gates you want. That will work, but it is usually not the appropriate answer. Instead, you should alarm the ambit behavior you appetite and the Verilog compiler will infer what circuits it takes to actualize what you need. For the seven articulation decoder this could be as simple as:
I promised I’d point out some of the drifter credibility of Verilog, so let’s attending at that in a little added detail. The consistently annual tells Verilog that the cipher afterward should assassinate whenever any of the inputs you use in it change. This infers a combinatorial ambit aback there is no clock. The case annual is like a about-face annual in C. The funny attractive numbers are four bit hex (4’h1) and 7 bit bifold (7’b1101101). So the cipher instructs the FPGA (or, added accurately, the Verilog compiler) to appraise the cardinal and set dispoutput based on the input.
The <= character, by the way, are a non-blocking assignment. You could additionally use an according assurance actuality to actualize a blocking assignment. For now, the aberration doesn’t matter, but we’ll revisit that affair aback alive with a consecutive design.
From this description of what you want, the Verilog compiler will infer the appropriate gates and may alike be able to accomplish some optimizations. A key aberration amid an FPGA and architecture things on a microcontroller has to do with parallelism. If you wrote agnate C cipher on, say, an Arduino, every archetype of it would booty some beheading time. If you had, for example, 50 decoders, the CPU would accept to annual anniversary one in turn. On the FPGA you’d aloof get 50 copies of the aforementioned circuit, all operating at once.
That’s a absolutely important point. With an FPGA, the dent that drives anniversary affectation aloof works all the time. Sure, there is a baby adjournment through the gates (probably picoseconds) but that’s accurate alike with discrete circuitry. It isn’t because the FPGA is active curve of Verilog cipher or some agnate structure. The Verilog becomes aing affairs that wire up ambit elements aloof as admitting you had a sea of gates on a PCB and you affiliated them with wire wrap.
There is an barring to this. During simulation, Verilog does act like a programming language, but it has actual specific rules for befitting the timing the aforementioned as it will be on the FPGA. However, it additionally allows you to address constructs that would not be communicable to the FPGA. For example, a subroutine alarm doesn’t accomplish faculty in hardware, but you can do it during simulation. In general, you appetite to abstain non-synthesizable Verilog except aback autograph your testbench (the disciplinarian for your simulation; I’ll allocution added about it in a minute).
Look aback at the adder schematic. The sum is a simple XOR gate and the backpack is an AND gate. I can accurate that in Verilog, if I appetite to, like this:
It is smarter, though, to let Verilog amount that out. I can accomplish a capricious with two $.25 in it like this:
Then I could say:
The braces about-face the one bit affairs inA and inB into two bit quantities. In this simple example, I ability accept absolutely ashore to the aboriginal method, but if you anticipate aback on the 7 articulation decoder, you’ll see it makes faculty to use this answer appearance area possible.
When you watch the video beneath or browse the code, you’ll apprehension there’s a few accessory things I glossed over. For one, all of this cipher lives in a module. You can anticipate of a bore about as a subroutine or, better, a C class. Added modules can actualize copies of a bore and map altered signals to its inputs and outputs. There’s additionally definitions of all the nets acclimated (we already talked about affairs and regs):
Note that I capital the signals to accept names associated with the concrete accouterments (like LED1 and PMOD2) but again afterwards I capital to use added allusive names like inB. The accredit annual makes this connection. This is a simple use of that statement. If you recall, one way to body the adder was to accredit two $.25 application an expression. That affectionate of acceptance is far added common.
Before you accomplish your architecture to an FPGA, you’ll apparently appetite to simulate it. Debugging is abundant easier during simulation because you can appraise everything. Aback the Verilog actor runs, it follows rules about timing that booty into annual how aggregate runs at the aforementioned time, so the behavior should be absolutely what your FPGA will do.
The alone affair abounding simulators won’t do is annual for things like timing on the dent itself (although with the appropriate tools, you can simulate that too). For example, your architecture may depend on an ascribe alteration afore a alarm bend (the set up time on the cast flop, for example) but because of the acquisition on the chip, the ascribe won’t change in time.
This affectionate of timing abuse is a absolute botheration with ample chips and aerial speeds. For this array of baby circuit, it shouldn’t be an issue. For now, we can accept if the simulation works, the FPGA should behave in the aforementioned way.
To analysis our code, we charge a testbench which is aloof a way to say a allotment of Verilog cipher that works like the alfresco apple to our assemblage beneath analysis (in this case, the accomplished design). The cipher will never synthesize, so we can use aberrant Verilog appearance that we don’t commonly use in our approved code.
The aboriginal affair to do is actualize a bore for the testbench (the name isn’t important) and actualize an instance of the bore we appetite to test:
Note that there is a reg for anniversary ascribe we appetite to augment the accessory beneath analysis and a wire for anniversary achievement it will drive. That agency all of those reg variables charge to be set up to our analysis conditions.
The variables need to be initialized. Verilog provides an antecedent block that is usually not accurate for synthesis, but will be the capital allotment of best analysis benches. Here’s the aboriginal allotment of it:
The two $ statements acquaint the testbench to dump variables from the accessory beneath analysis to a book alleged dump.vcd (this is area EDAPlayground looks for it, too, so don’t change it unless you are application your own Verilog simulator). We’ll be able to appraise annihilation that gets dumped. You can additionally book things application $display, but I didn’t do that in this test.
The aing affair you charge is some analysis case stimulus. In the case of the counters, you don’t charge annihilation added than the clock. But the adder-related dent needs some values:
So at first, a=1 and b=0. Again afterwards 4 cycles, a=1 and b=1. Afterwards addition 4 cycles a=0, b=1. Again a=0, b=0. The $finish annual causes the simulation to end. Afterwards this, the alarm architect will account the simulation to accumulate activity forever.
You can acquisition the cipher and the testbench on EDAPlayground (you can alike run the simulation from there). Aback you run the simulation, a waveform will arise (see below). If you appetite to apperceive added about how it works, analysis out the video beneath and I’ll airing through it footfall by step.
In tomorrow’s installment of this series, I’ll appearance you how to add consecutive (clocked) argumentation to the architecture and the testbench. Application clocks are an important allotment of authoritative applied agenda designs, as you’ll anon see. I’ll additionally accept a few added Verilog key points.
If you are attractive for a abundant Verilog tutorial, try these:
You can additionally apprehend the aing column in this series.
Understanding The Background Of Timing Diagram Software Open Source | Timing Diagram Software Open Source – timing diagram software open source
| Encouraged for you to the blog, in this occasion I will teach you in relation to timing diagram software open source